Field of the Invention
The present invention relates to a voltage detection circuit, and more specifically to a reduction in the influence of manufacturing variations thereof.
Background Art
FIG. 7 is a circuit diagram illustrating one example of a related art voltage detection circuit.
NMOS transistors Q1 and Q2, NMOS transistors Q11 and Q12, and PMOS transistors Q3 and Q13 are respectively assumed to be the same size. A resistor R1 is made by, for example, a diffusion resistance or a gate POLY resistance. A voltage to be applied and a generated current indicate a proportional relation. A depletion type NMOS transistor R2 has a gate and a source connected to each other. When a drain-source voltage to be applied reaches a predetermined voltage or higher, the current becomes constant.
A current I1 which flows through the resistor R1 flows in the NMOS transistor Q2 as a drain current Is1 by a mirror circuit configured by the NMOS transistors Q1 and Q2. A current generated in the resistor R1 becomes small when a power supply voltage is small, and the current generated therein becomes large when the power supply voltage is large.
On the other hand, a current I2 which flows through a depletion type NMOS transistor R2 flows as a drain current Is2 of the PMOS transistor Q3 by mirror circuits respectively configured by the NMOS transistors Q11 and Q12 and the PMOS transistors Q3 and Q13. Since the depletion type NMOS transistor R2 hardly has drain voltage dependence in a saturation region, the drain current Is2 of the PMOS transistor Q3 does not change even when the power supply voltage changes.
The related art voltage detection circuit detects the power supply voltage using the relationship between the drain currents of the NMOS transistor Q2 and the PMOS transistor Q3 and the power supply voltage.